Concurrency - All the Way Down

std::atomic and std::memory_order are utterly opaque abstractions. It feels like they were put in place to hide some monstrosity that is too complex for mortals to comprehend, and inevitably when trying to understand the underlying reality, the explanations end with 'the processor does weird things' and 'you can think about it as if...'.

Well, 'think about it as if' no more. In this talk we'll present the gory and wonderful mechanics of cache coherence protocols, write buffers and invalidation queues. We'll explain how modern hardware design makes different cores have different views of memory, and what the instructions for fence and read-modify-write do exactly - for both x86/64 and ARM/RISC-V.

If time permits, we'll discuss futexes and OS-managed synchronization primitives, and how they are implemented in terms of atomics and fences. This is an advanced low-level talk, placed at the borderline of software development and electrical engineering, on topics never before surveyed at C++ conference talks.